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Flip Chip TVS Diode with T-Filter for Color LCD Interface Protection
PROTECTION PRODUCTS Description
The SFC2309-200 is a low pass filter array with integrated TVS diodes. It is designed to suppress unwanted EMI/RFI signals and provide electrostatic discharge (ESD) protection in portable electronic equipment. This state-of-the-art device utilizes solidstate silicon-avalanche technology for superior clamping performance and DC electrical characteristics. They have been optimized for protection of color LCD panels in cellular phones and other portable electronics. The device consists of ten identical circuits comprised of TVS diodes for ESD protection, and a resistor capacitor network for EMI/RFI filtering. A series resistor value of 200 and a capacitance value of 45pF is used to achieve 25dB minimum attenuation from 800MHz to 3GHz. Each line features two stages of TVS diode protection. The TVS diodes provide effective suppression of ESD voltages in excess of 15kV (air discharge) and 8kV (contact discharge) per IEC 61000-4-2, level 4. The device is a 25-bump, 0.5mm pitch flip chip array with a 5x5 bump grid. It measures 2.6 x 2.6 x 0.65mm. The solder bumps have a nominal diameter of 0.315mm.
SFC2309-200
PRELIMINARY
Features
Flip Chip bidirectional EMI/RFI filter with integrated ESD protection
ESD protection to IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) Filter performance: 25dB minimum attenuation 800MHz to 3GHz TVS working voltage: 5V Resistor: 200 Input Capacitance:45pF Protection and filtering for ten lines
Mechanical Characteristics
JEDEC MO-211, Variation BF, 0.50 mm Pitch Flip Chip Nominal Dimensions: 2.6 x 2.6 x 0.65 mm Bump Diameter: 31520 m Marking : Marking code, dot at ball A1 Packaging : Tape and Reel per EIA 481
Applications
Color LCD Panel Protection Cell Phone Handsets and Accessories Personal Digital Assistants (PDA's) Notebook & Hand Held Computers
Circuit Diagram
PIN Configuration
LOW PASS FILTER
CIN 45pF RS 200
Circuit 10x
Revision 06/11/03 1
5 x 5 Grid Flip Chip (Ball Side View)
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SFC2309-200
PROTECTION PRODUCTS Absolute Maximum Rating
R ating ESD p er IEC 61000-4-2 (Air) ESD p er IEC 61000-4-2 (Contact) Junction Temp erature Op erating Temp erature Storage Temp erature Symbol VESD TJ Top TSTG Value 15 12 125 -40 to +85 -55 to +150
PRELIMINARY
Units kV
o
C C C
o
o
Electrical Characteristics
SF C 2 3 0 9 - 2 0 0 P a r a met er T VS Reverse Stand-Of f Voltage T VS Reverse Breakdown Voltage T VS Reverse Leakage Current Total Series Resistance Total Capacitance Symb ol VRWM VBR IR R C in It = 1mA VRWM = 3.0V Each Line Input to Ground, Each Line VR = 0V, f = 1MHz 170 200 45 6 8 C on d i t i on s Mi n i mu m Ty p i c a l M a xi m u m 5 10 0.5 230 50 Un i ts V V A pF
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SFC2309-200
PROTECTION PRODUCTS Typical Characteristics
Typical Insertion Loss S21 (Each Line)
CH1
PRELIMINARY
Analog Crosstalk (Each Line)
CH1 S21 LOG 20 dB/ REF 0 dB
S21
LOG
6 dB/
REF 0 dB
Cor
Cor
START
. 030 000 MHz
STOP 3 000 . 000 000 MHz
START
. 030 000 MHz
STOP 3 000 . 000 000 MHz
ESD Clamping (8kV Contact)
50
Capacitance vs. Reverse Voltage
45
Capacitance - CJ (pF)
40
35
30
f = 1 MHz
25 0 1 2 3 4 5 6
Reverse Voltage - VR (V)
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SFC2309-200
PROTECTION PRODUCTS Applications Information
Device Connection Options The SFC2309-200 has solder bumps located in a 5 x 5 matrix layout on the active side of the device. The bumps are designated by the numbers 1 - 5 along the horizontal axis and letters A - E along the vertical axis. The input of the lines to be protected are connected at bumps A1 - A5 and B1 - B5. The line outputs are connected at bumps D1 - D5 and E1 - E5. Bumps C1 C5 are connected to ground. All path lengths should be kept as short as possible to minimize the effects of parasitic inductance in the board traces. Wafer Level CSP TVS CSP TVS devices are wafer level chip scale packages. They eliminate external plastic packages and leads and thus result in a significant board space savings. Manufacturing costs are minimized since they do not require an intermediate level interconnect or interposer layer for reliable operation. They are compatible with current pick and place equipment further reducing manufacturing costs. Certain precautions and design considerations have to be observed however for maximum solder joint reliability. These include solder pad definition, board finish, and assembly parameters. Printed Circuit Board Mounting Non-solder mask defined (NSMD) land patterns are recommended for mounting flip chip devices. Solder mask defined (SMD) pads produce stress points at the solder mask to solder ball interface that can result in solder joint cracking when exposed to extreme fatigue conditions. The recommended pad size is 0.275 0.010 mm with a minimum solder mask opening of 0.325 mm. Grid Courtyard The recommended grid placement courtyard is 2.7 x 2.7 mm. The grid courtyard is intended to encompass the land pattern and the component body that is centered in the land pattern. When placing parts on a PCB, the highest recommended density is when one courtyard touches another.
PRELIMINARY
Pin Identification and Configuration (Ball Side View)
Pin A1 - A5 B1 - B5 C1 - C5 D1 - D5 E1 - E5
Identification Inp ut, Lines 1, 2, 3, 4, 5 Inp ut, Lines 6, 7, 8, 9, 10 Ground Outp ut, Lines 6, 7, 8, 9, 10 Outp ut, Lines 1, 2, 3, 4, 5
Layout Example (Ball Side View)
1 6 2 7 Output 3 8 4 9 5 10
6
1
7
2
8
39 Input
4 10
5
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SFC2309-200
PROTECTION PRODUCTS Applications Information
Printed Circuit Board Finish A uniform board finish is critical for good assembly yield. Two finishes that provide uniform surface coatings are immersion nickel gold and organic surface protectant (OSP). A non-uniform finish such as hot air solder leveling (HASL) can lead to mounting problems and should be avoided. Stencil Design A properly designed stencil is key to achieving adequate solder volume without compromising assembly yields. A 0.100mmto 0.200mm thick, laser cut, electropolished stencil with 0.330mm apertures corners with rounded corners is recommended. Reflow Profile The flip chip TVS can be assembled using standard SMT reflow processes. As with any component, thermal profiles at specific board locations can vary & must be determined by the manufacturer. The flip chip TVS peak reflow temperature is 230 10 C for a maximum time of 10 seconds. Time above eutectic temperature (183 C) should be 50 10 seconds. During reflow, the component self-aligns itself on the pad. Solder Reflow Profile Recommended NSMD Pad and Stencil Aperture
PRELIMINARY
Circuit Board Layout Recommendations for Suppression of ESD Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: Place the TVS near the input terminals or connectors to restrict transient coupling. Minimize the path length between the TVS and the protected line. Minimize all conductive loops including power and ground loops. The ESD transient return path to ground should be kept as short as possible. Never run critical signals near board edges. Use ground planes whenever possible.
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SFC2309-200
PROTECTION PRODUCTS Applications Information
SFC2309-200
10 5 9 4 8 3 5 10 4 9 3 8 2 7 1 6
PRELIMINARY
Baseband Controller
7 2 6 1
LCD Display LCD Display
SFC2309-200
10 5 9 4 8 3 7 2 6 1 5 10 4 9 3 8 2 7 1 6
Implementation Example
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SFC2309-200
PROTECTION PRODUCTS Applications Information
Insertion Loss The insertion loss of the device is the ratio of the power delivered to the load with and without the filter in the circuit. This parameter is dependent upon the impedance of the source and the load. The standard impedance of test equipment that is used to measure filter frequency response is 50. In order to obtain an accurate measurement of the filter performance, an evaluation board with 50 transmission lines are used. The test conditions for the SFC2309-200 are shown below. The evaluation board contains SMA connectors at each of the circuits inputs and outputs. The connections are made with 50 traces. An HP 8753E network analyzer with an internal spectrum analyzer and tracking generator is used. This equipment has the capability to sweep the device from 3kHz to 3GHz. The analyzer's source (RS) impedance is equal to the load (RL) impedance which is equal to 50.
CH1
PRELIMINARY
S21 LOG 6 dB/ REF 0 dB
Cor
START
. 030 000 MHz
STOP 3 000 . 000 000 MHz
Insertion Loss S21
50 Ohms To Connector (Output) To Connector (Input)
50 Ohms Vg
Insertion Loss Measurement Conditions
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SFC2309-200
PROTECTION PRODUCTS Applications Information
SFC2309-200 Spice Model & Parameters
PRELIMINARY
Line In
Line Out
SFC2309-200 Spice Model
SFC2309-200 Spice Parameters Parameter IS BV VJ RS IB V CJO TT M N EG Unit Amp Volt Volt Ohm Amp Farad sec --eV D1 (T VS) 1E-14 7.1 0.62 0.124 1E-3 25E-12 2.541E-9 0.108 1.05 1.11 D2 (T VS) 1E-14 7.1 0.62 0.124 1E-3 25E-12 2.541E-9 0.108 1.05 1.11
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SFC2309-200
PROTECTION PRODUCTS Outline Drawing PRELIMINARY
Land Pattern
0.275
0.5
0.5
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SFC2309-200
PROTECTION PRODUCTS Marking PRELIMINARY Ordering Information
Part Number SFC2309-200.TC Series R esistor 200 Qty per Reel 3000 R eel Size 7 Inch
Lotcode
Top View Showing Laser Mark
2309 -200
Add "T" suffix for lead free bumps. Ex: SFC2309-200.TCT
Tape and Reel Specification
Pin A1
SFC2309
SFC2309
SFC2309
SFC2309
SFC2309
-200
-200
-200
-200
-200
Tape Specifications
Device Orientation in Tape
Contact Information
Semtech Corporation Protection Products Division 200 Flynn Rd., Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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